1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming fins for FinFET semiconductor devices and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a perspective view of an illustrative prior art integrated circuit product 100 that is formed above a semiconductor substrate 105. In this example, the product 100 includes five illustrative fins 110, 115, a shared gate structure 120, a sidewall spacer 125 and a gate cap 130. The product 100 implements two different FinFET transistor devices (N-type and P-type) with a shared gate structure. The gate structure 120 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the transistors on the product 100. The fins 110, 115 have a three-dimensional configuration. The portions of the fins 110, 115 covered by the gate structure 120 define the channel regions of the FinFET transistor devices on the product 100. An isolation structure 135 is formed between the fins 110, 115. The fins 110 are associated with a transistor device of a first type (e.g., N-type), and the fins 115 are associated with a transistor device of a complementary type (e.g., P-type). The gate structure 120 is shared by the N-type and P-type transistors, a common configuration for memory products, such as static random access memory (SRAM) cells.
Typically, fins are initially formed in a regular array across a substrate. To define separate transistor devices, the length of the fins may be adjusted and some fins or portions of fins may be removed. For example, a fin cut or “FC cut” process involves cutting or removing portions of fins beneath an opening defined in an FC cut mask. The long axis of the opening in the FC cut mask typically runs in a direction that is parallel to the width of the fins, i.e., the fins are “cross-cut” during the FC cut process. In contrast to the FC cut process, fins are also cut in what is referred to as an active region cut process, or “RX cut” process. In the RX cut process, the portions of the fins that are to remain are protected or covered by the RX cut mask. Thus, in the RX cut process, portions of the fins not protected by the RX cut mask are removed. For example, during the RX cut process, one or more of the fin segments (not covered by the RX cut mask) that are positioned between other parallel-positioned fin segments (that are covered by the RX cut mask) may be removed (e.g., one or more fins may be removed in the region between the fins 110 and the fins 115).
In the RX cut process, the dielectric material above the fin portions to be removed is removed to expose only the upper surface of the underlying fin portions that are to be removed. A subsequent isotropic etch process removes the exposed fin portions. An isotropic etch process is used to avoid alignment problems associated with anisotropic etch processes given the small pitch of the fins. Alignment errors may result in leaving unwanted portions of fins or damaging remaining fins if an anisotropic etch were to be used. Because only the top surface of the fin is exposed during the isotropic etch, the etch front moves generally vertically downward from the exposed top of the fin toward the substrate.
FIGS. 2A-2C are cross-section views of a device 200 showing a plurality of fins 205 defined above a substrate 210. The fins 205 may be defined using a variety of materials, such as silicon, an alloy of silicon, such as silicon germanium, or other semiconducting materials. In FIGS. 2A-2C, the cross-section is taken in a direction perpendicular to the long axis of the fins 205 (i.e., in the gate width direction of the device 200). An oxide cap layer 215 and a nitride cap layer 220 (previously used as hard mask layers to pattern the fins 205 in the substrate 210) are present above some of the fins 205. Liners 225, 230 may be formed above the fins 205. A dielectric layer 235 may be formed between the fins 205.
As shown in FIG. 2A, the cap layers 215, 220 and a portion of the dielectric layer 235 were selectively removed from above the fins 205 that are to be removed during the RX cut process. The cap layers 215, 220 remain positioned above the fins 205 that are to be retained.
FIG. 2B illustrates the device 200 after an isotropic etch process was performed to remove the fins 205 that are no longer covered by the cap layers 215, 220, thereby defining recesses 240 in the vacated regions.
FIG. 2C illustrates the device 200 after a deposition process was performed to form a dielectric layer 245 above the fins 205. In some cases, the dielectric layer 245 does not completely fill the recesses 240 thereby defining air gaps 250. During subsequent process steps, the dielectric layers 235, 245 are recessed to define an isolation structure between the remaining fins 205 and expose the sidewalls of the fins 205. After this recessing, the air gaps 250 are opened due to their height substantially being the same as the height of the fins 205. The air gaps 250 represent undesired trenches in the structure that may result in the creation of significant defects during subsequent processing, such as shorts.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.